In integrated circuit (IC) manufacturing, a wafer or otherwise generally round substrate passes through a number of different fabrication stages to form one or more integrated circuits thereon. The wafer is generally formed out of a semiconductor material, such as silicon, and may pass through the different stages one or more times to form multiple layers upon the wafer. Throughout the process, the wafer and layers are treated in various manners to establish one or more semiconductor modules and elements upon the wafer. These modules can be considered the building blocks of the integrated circuits, and may also comprise other modules, sub-modules and/or elements, such as transistors, for example. A static random access memory (SRAM) cell is one type of semiconductor module, for example, that comprises a plurality of transistors as well as other types of integrated circuit elements. After the fabrication process is complete, one or more integrated circuits generally exist upon discrete sections of the wafer, known as die. The individual die can then be removed (e.g., cut) from the wafer and sold to consumers (e.g., as semiconductor “chips”).
As noted, modules are made up of elements (e.g., transistors). It can be appreciated that variations within the fabrication process can affect element characteristics. Stated another way, variations of process conditions within the different fabrication stages can have an effect on the operating parameters and resulting performance of the elements and between elements. For example, varying (e.g., increasing) a process condition such as temperature, for example, at an annealing or heating stage of the fabrication process can, for example, facilitate a change in, among other things, a level of and/or rate of diffusion of a dopant substance in an element produced by the fabrication process (e.g., enhancing the level and/or rate of diffusion), whereby an operating parameter of the element, such as a switching speed of the element, for example, is resultantly altered (e.g., accelerated).
It can be appreciated that some variations within the fabrication process, or rather some variations of process conditions at the different stages of the fabrication process, can have a substantially uniform effect upon one or more elements fabricated thereby. For example, the operating parameter of threshold voltage (Vt) of a transistor type element is a function of multiple characteristics of the transistor, such as gate oxide thickness (tox) as well as level of channel doping, for example, where gate oxide thickness and channel doping are themselves a function of one or more process conditions at one or more fabrication stages.
Gate oxide thickness may, for example, be a function of a flow rate, temperature and/or viscosity, etc. of a substance applied to a wafer in establishing a layer of gate oxide material at a particular stage of the fabrication process, for example. A change in one or more of these process conditions will likely have the same effect on the thickness of the gate oxide layer across the entirety of the wafer or any resulting variations in the thickness of the gate oxide layer across the wafer will be gradual such that there will be substantially no resulting variation in thickness among elements that are in the same proximity. Accordingly, such variations in process conditions may be referred to as global variations since they have a substantially uniform effect upon the characteristic of gate oxide thickness (tox) and the operating parameter Vt across the wafer, or at least within a module. Similarly, uniform or gradual changes in characteristics, such as tox, for example, across a wafer can be referred to as global variations, and the effect of such global variations on similar elements within a module can be approximated to be the same. Also, element parameters, such as the aforementioned component of threshold voltage Vt, that vary as a result of other global variations can likewise be referred to as global variations.
As applied to an SRAM cell, for example, a global variation in the electrical characteristics of the elements will cause a variation in the operating parameters of the SRAM cell, such as static noise margin (SNM) and trip voltage (Vtrip). Exercising control over one or more process conditions to limit the global variation of the characteristics of the circuit elements (e.g., transistors) may in turn limit the range of operating parameters (e.g., SNM and/or Vtrip) of the SRAM cell incurred from the global variation of the circuit elements. If the global variation is essentially uniform across a die, then SRAM cells on a die will have the same operating parameters as influenced by the global characteristics of the elements.
To minimize power for a given required level of performance in an SRAM, one approach is to monitor the speed of example circuits, such as a ring oscillator, and lower the operating voltage if the frequency of the monitored circuit is above some predetermined frequency, or to raise the operating voltage if the frequency of the monitored circuit is below some predetermined frequency. This technique allows a lower voltage for “fast” silicon, saving power. That is, a chip with lower NMOS threshold voltage (Vtn) and/or a lower PMOS threshold voltage (Vtp) can run with a lower operating voltage.
However, SRAM functionality, such as static noise margin (SNM) and trip voltage (Vtrip), depends on the ratio of transistors as well as the magnitude of the Vt's. For example, the SNM of an SRAM cell depends on the ratio of the pass gate transistor to the driver transistor as well as the Vt of the driver transistor. The trip voltage Vtrip depends on the ratio of the pass gate to the load transistor as well as the threshold voltage Vt of the driver and the threshold voltage of the load transistor. Thus, because of Vtrip requirements, a chip having SRAM with a low Vtp and a nominal Vtn may not be able to run at as low an operating voltage as would be allowed for the logic portion of the chip, based on frequency requirements for the logic. Similarly, a minimum operating voltage Vmin for a chip with a low Vtn might be limited by the SNM requirements of the SRAM.
Another problem in determining an acceptable operating voltage for SRAM is that the minimum operating voltage will vary from cell to cell within an array due to random variation among the transistors. Such, variations that affect individual elements or cells differently can be referred to as local variations among the local parameters between elements or cells, for example. Thus, if measurements are made on a few transistors representing the transistors in a memory array, those transistors may not be typical of the array. Also, the transistors most likely will not represent the worst case cell among the many cells in an array, or a corresponding minimum operating voltage required for such cells.
In view of such global and local variations, a quantification of the performance, robustness or reliability of an SRAM device may be utilized which may be referred to as figure-of-merit (FOM) of an integrated circuit module, where the FOM of the module may be described in terms of a distribution of an operating parameter of the fabricated module, for example, such as noise margin (SNM) or trip voltage (Vtrip) for an SRAM cell.
It can thus be appreciated that element characteristics and resulting operating parameters of the elements are affected by both global and local variations where the elements are uniformly affected by the global variations but are affected on a more individual basis by the local variations. Because of these factors, setting a suitable operating voltage for SRAM is challenging in view of the numerous global and local variations which affect SRAM performance.
Thus, it would be desirable to be able to determine and set the operating voltages of an SRAM device for both Vtrip and SNM in a manner that reduces power while maintaining functionality and performance of the device.